Using present semiconductor device technology, problems arise as semiconductor devices are scaled to smaller dimensions due to hot carriers and the associated changes in device characteristics during device operation.
Generation of hot carriers increases as the electric field in the semiconductor devices increases. In current semiconductor technology, a common approach for reducing generation of hot carriers is to reduce the magnitude of the electric field in the appropriate region of high electric field. The reduction of the electric field reduces the kinetic energy of the carrier, and therefore limits the number of high energy, "hot", carriers in the semiconductor device.
In present MOSFET technology, the reduction of the magnitude of the electric field in the appropriate region of the semiconductor device has been attempted using three main approaches. First, conventional dopant impurities, such as arsenic, phosphorous, or boron, of a type opposite to that of the well dopant are introduced to form a lightly doped spacer region (LDD) near the more heavily doped source/drain regions. Second, external bias voltages can be reduced. Third, structural changes in the basic MOSFET structure have been considered such as increased gate oxide thickness between the MOSFET gate and source/drain regions to reduce the electric field in these regions.
Several problems exist in the present techniques for reducing hot carrier generation and associated changes in device characteristics by means of reducing the electric field. The introduction of a lightly doped spacer region will increase the parasitic resistance, increase the susceptibility of variations in the device characteristics during operation due to changes in the parasitic resistance caused by the hot carriers, and constrain the design of devices due to the amount of area needed for the spacer region to effectively reduce hot carrier generation.
The other two methods which are currently used to reduce hot carrier generation also have problems. Reducing the external bias voltage will increase the susceptibility of the device to external noise and decrease the speed of the device. Structural modifications are not practical or possible for every device, and at least some device degradation occurs in the devices where the modifications are possible. For example, in most MOSFET devices, the thickness of the oxide between the gate and the drain/source could be increased, by thermal oxidation, to reduce the generation of the hot carriers. This process is not very controllable and could, therefore, degrade the device by reducing the current flow.